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Triple Modular Redundancy (TMR) has traditionally been used for protecting digital logic from the SEUs in space born applications. The main usage has been either on module level or for the protection of sequential elements in digital logic. A very simple method to implement SEU mitigation in an FPGA design is to replicate redundant instances of an entire module and vote on the module's final outputs. In this context a module can represent the entire design of a particular device or its subcomponent. This is a very effective means of SEU mitigation that is easy to implement and can be done entirely within a single FPGA device as long as the module uses no more than a third of the total device.

Triple device redundancy and mitigation is an alternative method that has the highest reliability for detecting single and multiple event disturbances, multiple transient disturbances, and any other functional interruptions including total device failure.

NHTMR has been designed to work with FPGAs and ASICs and is therefore based on device redundancy. The redundancy of the device can be managed by hardware (FPGA) or by software through communication on multiple ports of various types.

 

 

 

 

X+

X-

Y+

Y-

Z+

Z-

A

H

H

H

H

VH

L

B

H

H

M

H

H

H

C

H

H

H

L

H

H

D

H

H

H

H

VH

L

NHTMR = B + C + ( A || D )

NHTMR OPTIMIZED SHIELDING ( SINGLE RADIATION SOURCE )

 

 

 

 

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